Nacho Navarro
- Computer Architecture Department at Universitat Politecnica de Catalunya (UPC)
- Barcelona Supercomputing Center (BSC)

Address: Jordi Girona 3, modul C6-209,
08034 Barcelona, Spain
Phone: +34 690 951 589
Email: nacho @ ac.upc.edu , nacho @ bsc.es

Prof. Nacho J. Navarro is actually Associate Professor at the Universitat Politecnica de Catalunya (UPC), Barcelona, Spain, the leader of the Accelerators for HPC at the Barcelona Supercomputing Center, and the managing director of the BSC/UPC NVIDIA CUDA Center of Excellence.

His first position at UPC was Lecturer starting October 1985. He received the M.S. and Ph.D. degree in Computer Science, Barcelona School of Informatics (FIB), from the Universitat Politecnica de Catalunya (UPC) in 1985 and 1991 respectively.

From 1983 he joined the Computer Architecture Department (Departament d’Arquitectura de Computadors) at UPC, and in 2005 the Barcelona Supercomputing Center (BSC), where he is actually the manager of the Accelerators for High Performance Computing group. Since 1994, he is Associate Professor at the Computer Architecture Department at UPC, where he teaches on operating systems and runtime support for new parallel computer architectures. He organizes the internationally renowned Programming and Tuning Massively Parallel Systems summer school (PUMPS), every July since 2010.

His current research interests include: GPGPU computing, multi-core computer architectures, hardware accelerators, dynamic reconfigurable logic support, memory management and runtime optimizations, operating systems for multi-cores, power management and resource management in heterogeneous environments, and also tracing and visualization tools.

His work has been published in international conferences in computer architecture and operating systems (ISCA, SC, ICS, ASPLOS, MICRO, IPDPS, ICPP, PACT, DAC, HiPEAC, EWOMP, ISPASS and USENIX). Nacho is a member of the IEEE, the IEEE Computer Society, the ACM and the European HiPEAC Network of Excellence.

Since 2001, he also holds a Visiting Research Professor position at the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign, USA, where he has been doing research in optimization of runtime systems for reconfigurable embedded architectures and GPU accelerators (Wen-mei Hwu IMPACT group), and at the C2S2 and GSRC projects funded under the Focus Center Research Program of the Semiconductor Research Corporation.

Nacho serves on the board of the HiPEAC EU Network of Excellence, and previously at the Spanish Association of Informatics (ATI, Spain) and the Spanish UNIX Users Group. From 1991 to 2004 he was researcher at the European Center for Parallelism of Barcelona (CEPBA) and the C4 (Computing and Communications Center of Catalonia). He was also co-founder of the first Spanish Internet provider Goya Servicios Telematicos, that later joined EUnet.

ACTIVITIES

- Managing Director of the BSC/UPC NVIDIA CUDA Center of Excellence, 2012-current
- Serves on the Steering Committee of the HiPEAC EU Network of Excellence, 2004-current
- Organizer of the Programming and Tuning Massively Parallel Systems summer school (PUMPS), BSC/UPC, 2010-current

PROGRAM CHAIR AND TECHNICAL PROGRAM COMMITTEES

- General Chair at the High Performance Embedded Architectures and Compilers, First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005
- Program Chair at MATEO12: Multicore Architectures and Their Effective Operation 2012, Barcelona, June 2012

Served at the Program Committees of these conferences, workshops and journals, among others:

- ICS: International Conference on Supercomputing
- SC: ACM/IEEE Conference on Supercomputing
- ISCA: IEEE/ACM International Symposium on Computer Architecture
- MICRO: IEEE/ACM International Symposium on Microarchitecture
- CGO: IEEE/ACM Int. Symposium on Code Generation and Optimization
- PACT: Int. Conf. on Parallel Architectures and Compilation Techniques
- TPDS: IEEE Transactions on Parallel and Distributed Systems
- TACO: ACM Transactions on Architecture and Compiler Optimization
- INPAR: Innovative Parallel Computing
- GPGPU: Workshop on General Purpose Processing Using GPUs
- SAMOS, Embedded Computer Systems: Architectures, Modeling, and Simulation, IEEE International Conference
- WIOSCA, Workshop on the Interaction between Operating Systems and Computer Architecture
- WRC: Workshop On Reconfigurable Computing
- EXADAPT: International Workshop on Adaptive Self-tuning Computing Systems for Exaflop Era
- MULTIPROG: Programmability Issues for Heterogeneous Multicores
- HeteroPar: Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms