Nacho Navarro Research Group Publications

Recent Publications

  • The AXIOM Software Layers, Carlos Alvarez; Eduard Ayguade; Javier Bueno; Antonio Filgueras; Daniel Jimenez-Gonzalez; Xavier Martorell; Nacho Navarro; Dimitris Theodoropoulos; Dionisios Pnevmatikatos; Davide Catani; Claudio Scordino; Paolo Gai; Carlos Segura; Carles Fernandez; David Oro; Javier Rodriguez-Saeta; Pierluigi Passera; Alberto Pomella; Antonio Rizzo and Roberto Giorgi, DSD 2015, 18th Euromicro Conference on Digital Systems Design (DSD), August 26-28, 2015
  • Coherence Protocol for Transparent Management of Scratchpad Memories in Shared Memory Manycore Architectures, Lluc Alvarez (BSC/UPC), Lluis Vilanova (BSC/UPC), Miquel Moreto (BSC), Marc Casas (BSC), Marc Gonzalez (UPC), Xavier Martorell (BSC/UPC), Nacho Navarro (BSC/UPC), Eduard Ayguade (BSC/UPC), and Mateo Valero (BSC/UPC), ISCA 2015, June 2015
  • Automatic Parallelization of Kernels in Shared-Memory Multi-GPU Nodes, Javier Cabezas (BSC), Lluis Vilanova (BSC), Isaac Gelado (NVIDIA Research), Thomas B. Jablin (UIUC), Nacho Navarro (BSC), Wen-mei Hwu (UIUC). ICS 2015, CA. June 2015
  • Hardware-Software Coherence Protocol for the Coexistence of Caches and Local Memories, Lluc Alvarez, Lluis Vilanova, Marc Gonzalez, Xavier Martorell, Nacho Navarro and Eduard Ayguade, IEEE Transactions on Computers, pp. 152-165, vol. 64, no. 1, Jan 2015. (ISSN: 0018-9340)
  • GPU-SM: shared memory multi-GPU programming, Javier Cabezas, Marc Jordà, Isaac Gelado, Nacho Navarro and Wen-Mei Hwu, GPGPU-8, 8th Workshop on General Purpose Processing Using GPUs, pp. 13-24, San Francisco, CA (United States), February 2015. (ISBN: 978-1-4503-3407-5)
  • Analyzing performance improvements and energy savings in Infiniband Architecture using network compression, Branimir Dickov, Miquel Pericas, Paul Carpenter, Nacho Navarro, Eduard Ayguade, SBAC-PAD 2014, In International Symposium on Computer Architecture and High Performance Computing, pp. 73-80, Paris (France), Oct 2014. (ISBN: 1550-6533)
  • Software-Managed Power Reduction in Infiniband Links, Branimir Dickov, Miquel Pericas, Paul M. Carpenter, Nacho Navarro, Eduard Ayguadé, In 2014 International Conference on Parallel Processing (ICPP-2014), pp. 311-320, Minneapolis (United States), Sep 2014. (ISBN: 978-1-4799-5618-0) pdf
  • Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors,Victor Garcia, Alejandro Rico, Carlos Villavieja, Paul Carpenter, Nacho Navarro and Alex Ramirez, OMHI 2014, Third International Workshop On-chip memory hierarchies and interconnects: organization, management and implementation, Porto (Portugal), Aug 2014. Best paper award. (ISBN: 978-3-319-14312-5)
  • Automatic execution of single-GPU computations across multiple GPUs, Javier Cabezas, Lluís Vilanova, Isaac Gelado, Thomas B. Jablin, Nacho Navarro, Wen-mei Hwu, In 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT 2014), Poster Session, pp. 467-468, Edmonton, AB (Canada), Aug 2014. (ISBN: 978-1-4503-2809-8). DOI=10.1145/2628071.2628109
  • Enabling Preemptive Multiprogramming on GPUs, Ivan Tanasic, Isaac Gelado (NVIDIA Research), Javier Cabezas, Alex Ramirez, Nacho Navarro, Mateo Valero, In 41st International Symposium on Computer Architecture (ISCA 2014), Minneapolis, MN (United States), Jun 2014.
  • CODOMs: Protecting Software with Code-centric Memory Domains, Lluís Vilanova, Muli Ben-Yehuda (Technion - Israel Institute of Technology), Nacho Navarro, Yoav Etsion (Technion – Israel Institute of Technology), Mateo Valero, In 41st International Symposium on Computer Architecture (ISCA 2014), Minneapolis, MN (United States), Jun 2014.
  • Experimental Assessment of a High Performance Back-end PCE for Flexgrid Optical Network Re-optimization, Lluís Gifre, Luis Velasco, Nacho Navarro, Gabriel Junyent, Optical Fiber Communication Conference and Exposition (OFC), March 2014.E-print UPC
  • Runtime and Architecture Support for Efficient Data Exchange in Multi-Accelerator Applications, Javier Cabezas, Isaac Gelado, John S Stone, Nacho Navarro, David B Kirk, Wen-mei W Hwu. IEEE Transactions on Parallel and Distributed Systems. April, 2014 IEEE Xplore
  • Auto-Tuning of Data Communication on Heterogeneous Systems, Marc Jorda, Ivan Tanasic, Luis Vilanova, Javier Cabezas, Isaac Gelado and Nacho Navarro, IEEE 7th International Symposium on Embedded Multicore/Many-core System-on-Chip (MCSoC’13), pp. 135-140, Tokyo (Japan), Sep 2013. (ISBN: 978-1-4799-1143-1)
  • Architecture of a Specialized Back-End High Performance Computing-Based PCE for Flexgrid Networks, Lluís Gifre, Luis Velasco, Nacho Navarro, 15th International Conference on Transparent Optical Networks (ICTON), June 2013. 10.1109/ICTON.2013.6602716
  • Comparison Based Sorting for Systems with Multiple GPUs, Ivan Tanasic, Lluís Vilanova, Marc Jorda, Javier Cabezas, Isaac Gelado, Nacho Navarro and Wen-mei W. Hwu, GPGPU-6 - Six Workshop on General Purpose Processing Using GPUs, Houston, TX (United States), Mar 2013.

Journals

  • TERAFLUX: Harnessing dataflow in next generation teradevices, Roberto Giorgi, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Guang R. Gao, Arne Garbade, Rahul Gayatri, Sylvain Girbal, Daniel Goodman, Souad Koliai, Mikel Lujan, Avi Mendelson, Laurent Morin, Nacho Navarro, Tomasz Patejko, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Ian Watson, Sebastian Weis, Stephane Zuckermann and Mateo Valero, Journal of Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), pp. 976-990, vol. 38, no. 8, Feb 2014. (ISSN: 0141-9331), April 2014. http://dx.doi.org/10.1016/j.micpro.2014.04.001
  • Runtime and Architecture Support for Efficient Data Exchange in Multi-Accelerator Applications, Javier Cabezas, Isaac Gelado, John E. Stone, Nacho Navarro, David B. Kirk, and Wen-mei Hwu, IEEE Transactions on Parallel and Distributed Systems, VOL. 25, 2014.
  • A systematic methodology to generate decomposable and responsive power models for CMPs, Ramon Bertran, Marc Gonzalez, Xavier Martorell, Nacho Navarro and Eduard Ayguade , IEEE Transactions on Computers, vol. 62 n. 7, pp. 1289 – 1302, Jul 2013. ISSN 0018-9340
  • A template system for the efficient compilation of domain abstractions onto reconfigurable computers, Muhammad Shafiq, Miquel Pericas, Nacho Navarro and Eduard Ayguade, Journal of Systems Architecture: the EUROMICRO Journal, vol. 59 no. 2, pp. 91–102, Feb 2013. ISSN 1383-7621
  • Counter-Based Power Modeling Methods: Top-Down Vs. Bottom-Up Ramon Bertran, Marc González, Xavier Martorell, Nacho Navarro and Eduard Ayguade, The Computer Journal (Kalispell, Mont.), vol. 56 no. 2, pp. 198–213, Aug 2012, ISSN 0748-9331, Feb 2013. DOI: 10.1093/comjnl/bxs116. (ISSN: 0010-4620)
  • POTRA: a framework for building power models for next generation multicore architectures, Ramon Bertran, Marc González, Xavier Martorell, Nacho Navarro and Eduard Ayguade, ACM SIGMETRIC Performance Evaluation Review, pp. 427-428, vol. 40, no. 1, Jun 2012. (ISSN: 0163-5999 )
  • Energy accounting for shared virtualized environments under dvfs using pmc-based power models, Future Generation Computer Systems, Ramon Bertran, Yolanda Becerra, David Carrera, Vicenc Beltran, Marc Gonzalez, Xavier Martorell, Nacho Navarro, Jordi Torres, Eduard Ayguade, Future Generation Computing Systems journal, Elsevier, ISSN 0167-739X, DOI: 10.1016/j.future.2011.03.007. (Link)
  • Assessing Accelerator-Based HPC Reverse Time Migration, Mauricio Araya-Polo, Javier Cabezas, Mauricio Hanzich, Miquel Pericas, Felix Rubio, Isaac Gelado, Muhammad Shafiq, Enric Morancho, Nacho Navarro, Eduard Ayguade, Jose Maria Cela, Mateo Valero, IEEE Transactions on Parallel and Distributed Systems, pp. 147-162, January 2011 (vol. 22 no. 1), doi:10.1109/TPDS.2010.144
  • Local Memory Design Space Exploration for High-Performance Computing, Ramon Bertran, Marc Gonzàlez, Xavier Martorell, Nacho Navarro, and Eduard Ayguadé, , The Computer Journal, Mar 2010; 10.1093/comjnl/bxq026. (Abstract) (PDF)
  • Linux Kernel Compaction through Cold Code Swapping, Dominique Chanet, Javier Cabezas, Enric Morancho, Nacho Navarro and Koen De Bosschere , Transactions on High-Performance Embedded Architectures and Compilers, pp. 60-88, vol. 2, no. 2, Sep 2007. (ISSN: 1864-306X)
  • Beating In-Order Stalls with “Flea-Flicker” Two-Pass Pipelining, Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro and Wen-mei W. Hwu, IEEE Transactions on Computers, pp. 18-33, vol. 55, no. 1, Jan 2006. Special Issue on Embedded Systems, Microarchitecture, and Compilation Techniques in Memory . (ISSN: 0018-9340)

Recent PhD Dissertations

  • Isaac Gelado, On the Programmability of Heterogeneous Massively‐Parallel Computing Systems, Advisors: Nacho Navarro and Wen‐mei W. Hwu, Jul 2010. Currently: NVIDIA Research.
  • Carlos Villavieja, Hardware and Software Support for Distributed Shared Memory in Chip Multiprocessors, Advisors: Nacho Navarro and Alex Ramirez, Jan 2012. Currently: Google USA.
  • Muhammad Shafiq, Architectural Explorations for Streaming Accelerators with Customized Memory Layouts, Advisors: Miquel Pericas, Nacho Navarro and Eduard Ayguadé, May 2012.
  • Ramon Bertran, Energy Characterization Methodologies for CMP/SMT Processor Systems, Advisors: Marc González and Nacho Navarro. Dec 2014. Currently: IBM Watson.
  • Javier Cabezas, On the Programmability of Multi‐GPU Computing Systems, Advisors: Nacho Navarro and Wen‐mei W. Hwu, June 2015. Moving to: NVIDIA.

Other Highlighted Publications

  • Energy accounting for shared virtualized environments under DVFS using PMC-based power models, Ramon Bertran, Yolanda Becerra, David Carrera, Vicenç Beltran, Marc González, Xavier Martorell, Nacho Navarro, Jordi Torres and Eduard Ayguadé, Future Generation Computer Systems, pp. 337-490, vol. 28, no. 2, Dec 2012.
  • A template system for the efficient compilation of domain abstractions onto reconfigurable computers, Muhammad Shafiq, Miquel Pericàs, Nacho Navarro and Eduard Ayguadé, Journal of Systems Architecture, Dec 2012.
  • Hardware-software coherence protocol for the coexistence of caches and local memories, Lluc Alvarez, Lluís Vilanova, Marc González, Xavier Martorell, Nacho Navarro and Eduard Ayguadé, Supercomputing 2012 , Salt Lake City (United States), Nov 2012.
  • PPMC : Hardware Scheduling and Memory Management support for Multi Hardware Accelerators, Tassadaq Hussain, Miquel Pericàs, Nacho Navarro and Eduard Ayguadé, International Conference on Field Programmable Logic and Applications, Oslo (Norway), Aug 2012.
  • Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up, Ramon Bertran, Marc González, Xavier Martorell, Nacho Navarro and Eduard Ayguadé, Computer Journal, Aug 2012.
  • A Systematic Methodology to Generate Decomposable and Responsive Power Models for CMPs, Ramon Bertran, Marc González, Xavier Martorell, Nacho Navarro and Eduard Ayguadé, IEEE Transactions on Computers, no. 99, Apr 2012.
  • PPMC : A Programmable Pattern based Memory Controller, Tassadaq Hussain, Muhammad Shafiq, Miquel Pericàs, Nacho Navarro and Eduard Ayguadé, Applied Reconfigurable Computing (ARC), pp. 1-12, HongKong (China), Mar 2012.
  • Energy accounting for shared virtualized environments under dvfs using pmc-based power models, Ramon Bertran, Yolanda Becerra, David Carrera, Vicenç Beltran, Marc González, Xavier Martorell, Nacho Navarro, Jordi Torres and Eduard Ayguadé, Future Generation Computer Systems, pp. 457-468, vol. 28, no. 2, Feb 2012.
  • DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory, Carlos Villavieja, Vasileios Karakostas, Lluís Vilanova, Yoav Etsion, Alex Ramirez, Avi Mendelson, Nacho Navarro, Adrian Cristal and Osman Unsal, in Parallel Architectures and Compilation Techniques (PACT), Galveston Island (United States), Sep 2011.
  • FELI: HW/SW support for on-chip distributed shared memory in multicores, Carlos Villavieja, Yoav Etsion, Alex Ramirez, Nacho Navarro, August 2011, Euro-Par'11: Proceedings of the 17th international conference on Parallel processing - Volume Part I , Volume Part I
  • Design space exploration for aggressive core replication schemes in CMPs, Lluc Alvarez, Ramon Bertran, Marc Gonzalez, Xavier Martorell, Nacho Navarro, Eduard Ayguade, June 2011, HPDC '11: Proceedings of the 20th international symposium on High performance distributed computing
  • TARCAD: A template architecture for reconfigurable accelerator designs, Muhammad Shafiq, Miquel Pericas, Nacho Navarro, Eduard Ayguade, June 2011, SASP '11: Proceedings of the 2011 IEEE 9th Symposium on Application Specific Processors
  • Decomposable and Responsive Power Models for Multicore Processors using Performance Counters, Ramon Bertran, Marc Gonzalez, Xavier Martorell, Nacho Navarro, Eduard Ayguade, 24th International Conference on Supercomputing (ICS'10). June 1-4, 2010, Tsukuba, Japan
  • An Asymmetric Distributed Shared Memory Model for Heterogeneous Parallel Systems, I. Gelado. J.E. Stone. J. Cabezas, S. Patel, N. Navarro and W.W. Hwu, , 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'10), March 2010, Pittsburgh, PA
  • FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators, Muhammad Shafiq, Miquel Pericas, Nacho Navarro, Eduard Ayguade, August 2010, FPL '10: Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
  • Exploiting Memory Customization in FPGA for 3D Stencil Computations, Muhammad Shafiq, Miquel Pericàs, Raul de la Cruz, Mauricio Araya-Polo, Nacho Navarro and Eduard Ayguadé, The 2009 International Conference on Field-Programmable Technology (FPT'09), Sydney, December 2009.
  • Cetra: A trace and analysis framework for the evaluation of Cell BE systems, Julio Merino, Lluc Alvarez, Marisa Gil, Nacho Navarro, 2009 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2009), April, 2009, Boston, Massachusetts
  • Predictive Runtime Code Scheduling for Heterogeneous Architectures, V. Jimenez, I. Gelado, L. Vilanova, M. Gil, G. Fursin and N. Navarro, HiPEAC 2009 Conference (HiPEAC 2009), January2009, Paphos, Cyprus
  • CUBA: An Architecture for Efficient CPU/Co-processor Data Communication, I. Gelado, J.H. Kelm, S. Ryoo, S. Lumetta, N. Navarro and W.W. Hwu, 22nd International Conference in Supercomputing (ICS'08), June, 2008, Kos, Greece
  • CIGAR: Application Partitioning for a CPU/Coprocessor Architecture, John Kelm, Isaac Gelado, Mark Murphy, Nacho Navarro, Steve Lumetta and Wen-mei Hwu, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), September, 2007, Brasov, Romania
  • Beating in-order stalls with “flea-flicker” two-pass pipelining, Ronald Barnes, Erik Nystrom, John Sias, Sanjay Patel, Nacho Navarro, Wen-mei Hwu, , 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-36), p. 387, 2003
  • Implicit Parallel Programming Models for Thousand-Core Microprocessors, Wen-mei Hwu, Shane Ryoo, Sain-Zee Ueng, John H. Kelm, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel A. Mahesri, Stephanie C. Tsao, Nacho Navarro, Steve S. Lumetta, Matthew I. Frank, and Sanjay J. Patel, Proceedings of the 44th Annual Design Automation Conference (DAC), June 2007
  • Yolanda Becerra, Jordi Garcia, Toni Cortes, Nacho Navarro, “Java Virtual Machine: the key for accurated memory prefetching”, Proceedings of the International Conference on Software Engineering Research and Practice & Conference on Programming Languages and Compilers, SERP 2006, June 26-29, 2006, Volume 2, CSREA Press 2006, (ISBN 1-932415-91-2)
  • Yolanda Becerra, Toni Cortes, Jordi Garcia, Nacho Navarro, “Evaluating the importance of virtual memory for Java”, International Symposium on Performance Analysis of Systems and Software (ISPASS 2003)
  • Albert Serra, Nacho Navarro and Toni Cortes, DITools: Application-level Support for Dynamic Extension and Flexible Composition, USENIX Annual Technical Conference (USENIX'2000), pp. 225-238, San Diego, CA (United States), June 2000 (ISBN: 1-880446-22-7)
  • Marc Gonzalez, Albert Serra, Xavier Martorell, Jose Oliver, Eduard Ayguade, Jesús Labarta and Nacho Navarro, Applying Interposition Techniques for Performance Analysis of OpenMP Parallel Applications In 14th International Parallel and Distributed Processing Symposium (IPDPS'00), pp. 235-240, Cancun (Mexico), May 2000 (ISBN: 0-7695-0574-0)
  • Xavier Martorell, Eduard Ayguade, Nacho Navarro, Julita Corbalan, Marc Gonzalez and Jesus Labarta, Thread Fork/Join Techniques for Multi-level Parallelism Exploitation in NUMA Multiprocessors, International Conference on Supercomputing (ICS'1999), pp. 294-301, Rhodes (Greece), June 1999 (ISBN: 1-58113-164-X)
  • Eduard Ayguade, Xavier Martorell, Jesus Labarta, Marc Gonzalez and Nacho Navarro, Exploiting Multiple Levels of Parallelism in OpenMP: A Case Study, International Conference on Parallel Processing (ICPP'1999), pp. 172-180, Aizu-Wakamatsu (Japan), September 1999 (ISBN: 0-7695-0350-0)
  • Eleftherios Polychronopoulos, Xavier Martorell, Dimitrios Nikolopoulos, Jesús Labarta, Theodore Papatheodorou and Nacho Navarro, Kernel-Level Scheduling for the Nano-Threads Programming Model, International Conference on Supercomputing (ICS'98), pp. 337-344, Melbourne (Australia), July 1998 (ISBN: 0-89791-998-X)
  • Xavier Martorell, Jesús Labarta, Nacho Navarro and Eduard Ayguadé. Analysis of Several Scheduling Algorithms under the Nano-threads Programming Model. In 11th International Parallel Processing Symposium (IPPS'97), pp. 281-287, Geneva (Switzerland), Apr 1997. (ISBN: 1063-7133) (ISBN:0-8186-7792-9)

Workshops

  • Branimir Dickov, Miquel Pericàs, Nacho Navarro and Eduard Ayguadé, Row-interleaved streaming data flow implementation of Sparse Matrix Vector Multiplication in FPGA, 4th HiPEAC Workshop on Reconfigurable Computing (WRC 2010), January 2010, Pisa, Italy
  • Javier Cabezas, Mauricio Araya-Polo, Isaac Gelado, Nacho Navarro, Enric Morancho and José M. Cela, High-Performance Reverse Time Migration on GPU, In XXVIII International Conference of the Chilean Computer Society -­ XIII Workshop on Parallel and Distributed Systems (WSDP), Santiago de Chile (Chile), Nov 2009
  • J. Merino, I. Gelado and N.Navarro, Evaluation of the Cell BE SPU Scheduling for Multi-Programmed Systems 4th Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA 2008). July 2008, Beijing, China
  • C. Villavieja, I. Gelado, A. Ramirez and N. Navarro, Memory Management on Chip-MultiProcessors with on-chip Memories. 4th Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA 2008). July, 2008. Beijing, China
  • Isaac Gelado, Javier Cabezas, Lluis Vilanova, Nacho Navarro, The Cost of IPC: an Architectural Analysis Workshop on the Interaction between Operating Systems and Computer Architecture, WIOSCA 2007, Workshop at ISCA-34, June 2007.
  • Ramon Bertran, Marisa Gil, Javier Cabezas, Victor Jimenez, Lluis Vilanova, Enric Morancho, Nacho Navarro, Building a Global System View for Optimization Purposes. WIOSCA 2006, Boston, MA

Editor

  • Mateo Valero, Nacho Navarro, “Multicore: The View from Europe” IEEE Micro Special Issue, vol. 30, no. 5, pp. 2,4, Sept.-Oct. 2010, doi: 10.1109/MM.2010.93 ieeexplore
  • Taewhan Kim, Pascal Sainrat, Steven S. Lumetta, Nacho Navarro, “Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems”, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007 ACM 2007
  • Tom Conte, Mateo Valero, Nacho Navarro, Wen-mei W. Hwu and Theo Ungerer, “High Performance Embedded Architecture and Compilers”, Lecture Notes on Computer Science, no. 3793. Barcelona, Spain, November 2005. ISBN 3-540-30317-0